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1 of 21 description the DS1315 phantom time chip is a combination of a cmos timekeeper and a nonvolatile memory controller. in the absence of power, an external battery maintains the timekeeping operation and provides power for a cmos static r am. the watch keeps track of hundredths of seconds, seconds, minutes, hours, day, date, month, and year information. the last day of the month is automatically adjusted for months with fewer than 31 days, including leap year correction. the watch opera tes in one of two formats: a 12 - hour mode with an am/pm indicator or a 24 - hour mode. the nonvolatile controller supplies all the necessary support circuitry to convert a cmos ram to a nonvolatile memory. the DS1315 can be interfaced with either ram or rom without leaving gaps in memory. pin configurations pin configurations continued at end of data sheet. features ? real - time clock keeps track of hundredths of seconds, seconds, minutes, hours, days, date of the month, months, an d years ? automatic leap year correction valid up to 2100 ? no address space required to communicate with rtc ? provides nonvolatile controller functions for battery backup of sram ? supports redundant battery attachment for high - reliability applications ? full 10% v cc operating range ? +3.3v or +5v operation ? industrial ( - 40 c to +85c) operating temperature ranges available pin description x1, x2 - 32.768 khz crystal connection we - write enable bat1 - battery 1 input gnd - ground d - data input q - data output rom/ ram - rom/ram mode select ceo - chip enable output cei - chip enable input oe - output enable rst - reset bat2 - battery 2 input v cc0 - switched supply output v cc1 - power supply input 19 - 6080; rev 11/11 www.dalsemi.com p dip (300 mils) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v cc1 v cc0 bat2 rst oe cei ceo rom/ram x1 x2 we bat1 gnd d q gnd DS1315 DS1315 phant om time chip
DS1315 phantom time chip 2 of 21 ordering information part temp range voltage (v) pin - package top mark* DS1315 - 33+ 0c to +70c 3.3 16 p dip ( 300 mils) DS1315 336 DS1315n - 33+ - 40c to +85c 3.3 16 p dip (300 mils) DS1315 336 DS1315 - 5+ 0c to +70c 5 16 p dip (300 mils) DS1315 56 DS1315n - 5+ - 40c to +85c 5 16 p dip (300 mils) DS1315 56 DS1315e - 33+ 0c to +70c 3.3 20 tssop (4.4mm) DS1315e xxxx - 336 DS1315en - 33+ - 40c to +85c 3.3 20 tssop (4.4mm) DS1315e xxxx - 336 DS1315en - 33+t&r - 40c to +85c 3.3 20 tssop (4.4mm) DS1315e xxxx - 336 DS1315e - 5+ 0c to +70c 5 20 tssop (4.4mm) DS1315e xxxx - 56 DS1315en - 5+ - 40c to +85c 5 20 tssop (4.4mm) DS1315e xxxx - 56 DS1315en - 5+t&r - 40c to +85c 5 20 tssop (4.4mm) DS1315e xxxx - 56 DS1315s - 33+ 0c to +70c 3.3 16 so (300 mils) DS1315 336 DS1315sn - 33+ - 40c to +85c 3.3 16 so (300 mils) DS1315 336 DS1315s - 5+ 0c to +70c 5 16 so (300 mils) DS1315 56 DS1315sn - 5+ - 40c to +85c 5 16 so (300 mils) DS1315s 56 DS1315s - 5+t&r 0c to +70c 5 16 so (300 mils) DS1315s 56 + denotes a lead (pb) - free/rohs - compliant package . t&r = tape and reel. * a + symbol located anywhere on the top mark indicates a lead - free device. an n located in the bottom right - hand corner of the top of the package denotes an industrial device. xxxx can be any combination of characters.
DS1315 phantom time chip 3 of 21 figure 1 . block diagram
DS1315 phantom time chip 4 of 21 operation communication with the time chip is established by pattern recognition of a serial bit stream of 64 bits which must be matched by executing 64 consecutive write cycles containing the proper data on data in ( d). all accesses which occur prior to recognition of the 64 - bit pattern are directed to memory via the chip enable output pin ( ceo ). after recognition is established, the next 64 read or write cycles either extract or update data in th e time chip and ceo remains high during this time, disabling the connected memory. data transfer to and from the timekeeping function is accomplished with a serial bit stream under control of chip enable input ( cei ) , output enable ( oe ), and write enable ( we ). initially, a read cycle using the cei and oe control of the time chip starts the pattern recognition sequence by moving pointer to the first bit of the 64 - bit comparison register. next, 64 consecutive write cycles are executed using the cei and we control of the time chip. these 64 write cycles are used only to gain access to the time chip. when the first write cycle is executed, it is compared to bit 1 of the 64 - bit comparison register. if a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. if a match is not found, the po inter does not advance and all subsequent write cycles are ignored. if a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset. pattern recognition continues for a total of 64 write cycles as described above until all the bits in the comparison register have been matched. (this bit pattern is shown in figure 2). with a correct match for 64 bits, the time chip is enabled and data transfer to or from the timekeeping registers may proceed. the next 64 cycles will cause the time chip to either receive data on d, or transmit data on q, depending on the level of oe pin or the we pin. cycles to other locations outside the memory block can be in terleaved with cei cycles without interrupting the pattern recognition sequence or data transfer sequence to the time chip. a standard 32.768 khz quartz crystal can be directly connected to the DS1315 via pins 1 and 2 (x1, x2). the cry stal selected for use should have a specified load capacitance (c l ) of 6 pf. for more information on crystal selection and crystal layout considerations, refer to application note 58 : crystal considerations with maxim real - time cloc ks (rtcs) .
DS1315 phantom time chip 5 of 21 figure 2 . time chip comparison register definition note: the pattern recognition in hex is c5, 3a, a3, 5c, c5, 3a, a3, 5c. the odds of this pattern being accidentally duplicated and causing inadvertent entry to the phantom time chip are less than 1 in 10 19 .
DS1315 phantom time chip 6 of 21 nonvolatile controller operation the operation of the nonvolatile controller circuits within the time chip is determined by the level of the rom/ ram select pin. when rom/ ram is connected to ground, the controller is set in the ram mode and performs the circuit functions required to make cmos ram and the timekeeping function nonvolatile. a switch is provided to direct power from the battery inputs or v cci to v cco with a m aximum voltage drop of 0.3 volts. the v cco output pin is used to supply uninterrupted power to cmos sram. the DS1315 also performs redundant battery control for high reliability. on power - fail, the battery with the highest voltage is automatically switched to v cco . if only one battery is used in the system, the unused battery input should be connected to ground. the DS1315 safeguards the time chip and ram data by power - fail detection and write protection. power - fail detection occurs when v cci falls below v pf which is set by an internal bandgap reference. the DS1315 constantly monitors the v cci supply pin. when v cci is less than v pf , power - fail circuitry forces the chip enable output ( ceo ) to v cci or v bat - 0.2 volts for external ram write protection. during nominal supply conditions, ceo will track cei with a propagation delay. internally, the DS1315 aborts any data transfer in progress without changing any of the time chip registers and prevents futu re access until v cci exceeds v pf . a typical ram/time chip interface is illustrated in figure 3. when the rom/ ram pin is connected to v cco , the controller is set in the rom mode. since rom is a read - only device that retains data in the absence of power, battery backup and write protection is not required. as a result, the chip enable logic will force ceo low when power fails. however, the time chip does retain the same internal nonvolatility and write protection as d escribed in the ram mode. a typical rom/time chip interface is illustrated in figure 4. figure 3 . DS1315 - to - ram/time chip interface
DS1315 phantom time chip 7 of 21 figure 4 . rom/time chip interface time chip register informati on time chip information is contained in eight registers of 8 bits, each of which is sequentially accessed 1 bit at a time after the 64 - bit pattern recognition sequence has been completed. when updating the time chip registers, each must be handled in grou ps of 8 bits. writing and reading individual bits within a register could produce erroneous results. these read/write registers are defined in figure 5. data contained in the time chip registers is in binary coded decimal format (bcd). reading and writing the registers is always accomplished by stepping though all eight registers, starting with bit 0 of register 0 and ending with bit 7 of register 7. am / pm/12/24- mode bit 7 of the hours register is defined as the 12 - or 24 - hour mode select bit. when high , the 12 - hour mode is selected. in the 12 - hour mode, bit 5 is the am/pm bit with logic high being pm. in the 24 - hour mode, bit 5 is the 20- hour bit (20 - 23 hours). oscillator and reset bits bits 4 and 5 of the day register are used to control the r eset and oscillator functions. bit 4 controls the reset pin input. when the reset bit is set to logic 1, the reset input pin is ignored. when the reset bit is set to logic 0, a low input on the reset pin will cause the time chip to abort data transfer with out changing data in the timekeeping registers. reset operates independently of all other in - puts. bit 5 controls the oscillator. when set to logic 0, the oscillator turns on and the real time clock/calendar begins to increment.
DS1315 phantom time chip 8 of 21 zero bits registers 1, 2, 3, 4, 5, and 6 contain 1 or more bits that will always read logic 0. when writing these locations, either a logic 1 or 0 is acceptable. figure 5 . time chip register definition
DS1315 phantom time chip 9 of 21 absolute maximum ratings voltage range on an y pin relative to ground - 0.3v to + 6 .0v operating temperature range, commercial 0c to +70c operating temperature range, industrial - 40 c to +85c storage temperature range - 55c to +125c soldering temperature (reflow) +260c lead temperature (soldering, 10 s ) +260c this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods of time may affect reliability. recommended operating conditions (t a = over the operating range.) parameter symbol min typ max units notes power - supply voltage operation 5v v cc 4.5 5.0 5.5 v 1 3.3v 3.0 3.3 3.6 input logic 1 v ih 2.2 v cc + 0.3 v 1 input logic 0 v il - 0.3 +0.6 v 1 battery voltage v bat1 or v bat2 v bat1, v bat2 2.5 3.7 v dc operating electrical characteristics (v cc = 5.0v 10%, t a = over the operating range.) parameter symbol min typ max units n otes average v cc power - supply current i cc1 6 ma 6 v cc power - supply current, (v cc0 = v cci - 0.3) i cc01 150 ma 7 ttl standby current ( cei = v ih ) i cc2 4 ma 6 cmos standby current ( cei = v cci - 0.2) i cc3 1.3 ma 6 input leakage current (any input) i il - 1 +1 a 10 output leakage current (any input) i ol - 1 +1 a output logic 1 voltage (i out = - 1.0 ma) v oh 2.4 v 2 output logic 0 voltage (i out = 4.0 ma) v ol 0.4 v 2 power - fail trip point v pf 4.25 4.5 v battery switch voltage v sw v bat1 , v bat2 13
DS1315 phantom time chip 10 of 21 dc power - down electrical characteristics (v cc < 4.5v, t a = over the operating range.) parameter symbol min typ max units notes ceo output voltage v ceo v cci - 0.2 or v bat1,2 - 0.2 v 8 v bat1 or v bat2 battery current i bat 0.5 a 6 battery backup current @ v cco = v bat - 0.2v i cco2 10 a 9 ac electrical operating characteristics rom/ ram = gnd (v cc = 5.0v 10%, t a = over the operating range.) parameter symbol min ty p max units notes read cycle time t rc 65 ns cei access time t co 55 ns oe access time t oe 55 ns cei to output low - z t coe 5 ns oe to output low - z t oee 5 ns cei to output high - z t od 25 ns oe to output high - z t odo 25 ns read recovery t rr 10 ns write cycle t wc 65 ns write pulse width t wp 55 ns write recovery t wr 10 ns 4 data setup t ds 30 ns 5 da ta hold time t dh 0 ns 5 cei pulse width t cw 55 ns oe pulse width t ow 55 ns rst pulse width t rst 65 ns ac electrical operating characteristics rom/ ram = v cco (v cc = 5.0v 10%, t a = over the operating range.) parameter symbol min typ max units notes read cycle time t rc 65 ns cei access time t co 55 ns oe access time t oe 55 ns cei to output lo w z t coe 5 ns oe to output low z t oee 5 ns cei to output high z t od 25 ns oe to output high z t odo 25 ns address setup time t as 5 ns address hold time t ah 5 ns read recov ery t rr 10 ns
DS1315 phantom time chip 11 of 21 parameter symbol min typ max units notes write cycle t wc 65 ns cei pulse width t cw 55 ns oe pulse width t ow 55 ns write recovery t wr 10 ns 4 data setup t ds 30 ns 5 data hold time t dh 0 ns 5 rst pul se width t rst 65 ns dc operating electrical characteristics (v cc = 3.3v 10%, t a = over the operating range.) parameter symbol min typ max units notes average v cc power - supply current i cc1 3 ma 6 average v cc power - supply current, (v cco = v cci - 0. 3) i cc01 100 ma 7 ttl standby current ( cei = v ih ) i cc2 2 ma 6 cmos standby current ( cei = v cci - 0.2) i cc3 1.1 ma 6 input leakage current (any input) i il - 1 +1 a output leakage current (any input) i lo - 1 +1 a output logic 1 voltage (i out = 0.4 ma) v oh 2.4 v 2 output logic 0 voltage (i out = 1.6 ma) v ol 0.4 v 2 power - fail trip point v pf 2.8 2.97 v battery switch voltage v sw v bat1 , v bat2 , or v pf 14 dc power - down electrical characteristics ( v cc < 2.97v, t a = over the operating range.) parameter symbol min typ max units notes ceo output voltage v ceo v cci or v bat1,2 - 0.2 v 8 v bat1 or v bat2 battery current i bat 0.5 a 6 battery backup current at v cco = v bat - 0.2 i cco 2 10 a 9
DS1315 phantom time chip 12 of 21 ac electrical operating characteristics rom/ ram = gnd (v cc = 3.3v 10%, t a = over the operating range.) parameter symbol min typ max units notes read cycle time t rc 120 ns cei access time t co 100 ns oe access time t oe 100 ns cei to output low - z t coe 5 ns oe to output low - z t oee 5 ns cei to output high - z t od 40 ns oe to output hi gh - z t odo 40 ns read recovery t rr 20 ns write cycle t wc 120 ns write pulse width t wp 100 ns write recovery t wr 20 ns 4 data setup t ds 45 ns 5 data hold time t dh 0 ns 5 cei pulse width t cw 100 ns oe pulse width t ow 100 ns rst pulse width t rst 120 ns
DS1315 phantom time chip 13 of 21 ac electrical operating characteristics rom/ ram = v cco (v cc = 3.3v 10%, t a = over the operating range.) parameter symbol min typ max units note s read cycle time t rc 120 ns cei access time t co 100 ns oe access time t oe 100 ns cei to output low - z t coe 5 ns oe to output low - z t oee 5 ns cei to output high - z t od 40 ns oe to output high - z t odo 40 ns address setup time t as 10 ns address hold time t ah 10 ns read recovery t rr 20 ns write cycle t wc 120 ns cei pulse width t cw 100 ns oe pulse width t ow 100 ns write recovery t wr 20 ns 4 data setup t ds 45 ns 5 data hold time t dh 0 ns 5 rst pulse width t rst 120 ns capacitance (t a = +25c) parameter symbol min typ max units notes input capacitance c in 10 pf output capacitance c out 10 pf
DS1315 phantom time chip 14 of 21 figure 6 . timing diagram: read cycle to time chip rom/ ram = gnd figure 7 . timing diagram: write cy cle to time chip rom/ ram = gnd
DS1315 phantom time chip 15 of 21 figure 8 . timing diagram: read cycle to time chip rom/ ram = v cco figure 9 . timing diagram: write cycle to time chip rom/ ram = v cco
DS1315 phantom time chip 16 of 21 figure 10 . timing diagram: reset pulse 5v device power - up/power - down characteristics rom/ ram = v cco or gnd (t a = 0c to +70c) parameter symbol min typ max units notes recovery time at power - up t rec 1.5 2.5 ms 11 v cc slew rate power - down v pf (max) to v pf (min) t f 300 s 11 v cc slew rate power - down v pf (min) to v sw t fb 10 s 11 v cc slew rate power - up v pf (min) to v pf (max) t r 0 s 11 cei high to power - fail t pf 0 s 11 cei propagation delay t pd 5 ns 2, 3, 11 figure 11 . 5v power - up condition rst t rst
DS1315 phantom time chip 17 of 21 figure 12 . 5v power - down condition 3.3v d evice power - up power - down characteristics rom/ ram = v cco or gnd (t a = 0c to +70c) parameter symbol min typ max units notes recovery time at power - up t rec 1.5 2.5 ms 12 v cc slew rate power - down v pf (max) to v pf (min) t f 300 s 12 v cc slew rate power - up v pf (min) to v pf (max) t r 0 s 12 cei high to power - fail t pf 0 s 12 cei propagation delay t pd 10 ns 2, 3, 11
DS1315 phantom time chip 18 of 21 notes: 1) all voltages are referenced to ground. 2) measured with load shown in f igure 15. 3) input pulse rise and fall times equal 10ns. 4) t wr is a function of the latter occurring edge of we or ce in ram mode, or oe or ce in rom mode. 5) t dh and t ds are funct ions of the first occurring edge of we or ce in ram mode, or oe or ce in rom mode. 6) measured without ram connected. 7) i cco1 is the maximum average load current the DS1315 can supply to external memory. 8) applies to ceo with the rom/ ram pin grounded. when the rom/ ram pin is connected to v cco , ceo will go to a low level as v cci falls below v bat . 9) i cco2 i s the maximum average load current that the DS1315 can supply to memory in the battery backup mode. 10) applies to all input pins except rst . rst is pulled internally to v cci . 11) see figures 11 and 12. 12) see figures 13 and 14 . 13) v sw is determined by the larger of v bat1 and v bat2 . 14) v sw is determined by the smaller of v bat1 , v bat2 , and v pf . figure 13 . 3.3v power - up condition
DS1315 phantom time chip 19 of 21 figure 14 . 3.3v power - down condition fi gure 15 . output load
DS1315 phantom time chip 20 of 21 pin configurations (continued) package information for the latest package outline information and land patterns (footprints), go to www.maxim - ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package draw ings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 16 pdip p16+1 21 - 0043 16 tssop u20+1 21- 0066 90- 0116 16 so w16+2 21- 0042 90- 0107 20 - pin tssop x1 x2 we nc bat1 gnd nc d q gnd 9 1 2 3 4 5 6 7 8 10 20 19 18 17 16 15 14 13 12 11 v cc1 v cc0 bat2 nc rst oe nc cei ceo rom/ram 16 - pin so (300 mil) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v cc1 v cc0 bat2 rst oe cei ceo rom/ram x1 x2 we bat1 gnd d q gnd
DS1315 phantom time chip 21 of 21 maxim cannot assume re sponsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses a re implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated produc ts, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc revision history revision date description pages changed 11/11 u pdate d the features , ordering information , am/pm/12/24 - mode , absolute maximum ratings , and package information sections 1, 2, 7, 9, 20

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